1. Technical Field
The invention is related to time division multiplex video cassette recorders and the like which employ a random access memory, as opposed to serial shift registers or the like, to perform time base compression and expansion.
2. Description of the Related Art
Numerous methods are known for compacting video data and for reducing the bandwidth of video data in a video cassette recorder or other devices. Among these techniques are: splitting the video signal into high and low frequency bands and transmitting the bands separately (U.S. Pat. No. 4,068,258); differentially encoding the luminance and two chrominance components into a single video word and transmitting the single video word (U.S. Pat. No. 4,129,882); time division multiplexing luminance and chrominance components, as in a video camera output video format (U.S. Pat. No. 4,163,247).
Video time division multiplexing has been implemented using serial shift registers or first-in, first-out (FIFO) structures (U.S. Pat. No. 4,396,937). An improvement has been to eliminate the serial shift register or FIFO structure and substitute instead a random access memory or the like to perform the time base compression and expansion required in time division multiplexing. However, since successive video lines must be loaded and unloaded simultaneously for continuous data flow, two memories are required, instead of one, in a so-called "double buffered" memory structure such as that described in U.S. Pat. No. 4,472,745. In the double buffered memory time compression technique, successive video lines are loaded into and read out of two memories in alternate succession so that each memory is being loaded while the other is being unloaded at any one given time. Double buffering to achieve time base compression is a well-known technique (U.S. Pat. No. 4,467,368) and is useful in other applications such as time base error correction (U.S. Pat. No. 4,394,686) and field sequential video signal transmission (U.S. Pat. No. 4,163,248).
Random access memories are also useful in video signal processors for superimposing a pilot signal onto the video signal. This may be performed by interleaving and de-interleaving alternate video words stored in the memory with data words representing the pilot signal (U.S. Patent No. 4,138,694).
While random access memories are now a relatively old technology, dual-port random access memories have recently become available commercially, as described in Advance Information/IDT 7130S/IDT 7130L, Integrated Devices Technology, Inc., 3236 Scott Blvd., Santa Clara, Calif., 1985. Such dual-port random access memories do not appear to be useful in video signal multiplexing, because as they are limited to a maximum byte access frequency of about 11 MHz, according to published specifications. In contrast, video signal processing for time division multiplexing requires on the order of 18 MHz to achieve reasonable sampling rates.
3. Problem
It would be preferrable to use random access memories, as opposed to serial shift registers or FIFO structures, to perform time base compression and expansion in video time division multiplexing. A random access memory is more versatile and can facilitate additional features, if desired (such as noiseless still-frame playback and multi-channel split-screen displays, for example). However, as previously described, in order to time compress a single video signal, such as the luminance component signal, two random access memories are required and a double buffering technique must be employed to permit the simultaneous loading and unloading of successive video lines of data for continuous data flow. Even with two memories, the system is vulnerable to loss of data due to conflicts between successive read and write operations in each memory caused by time base errors in the incoming video signal. Such data losses are avoided in the prior art by introducing a spare third memory which is pulled into action whenever a time base error occurs. A typical double buffering structure would include two memories A and B and a spare memory C which is available in case of time base errors.
In one example, video line 1 is unloaded from memory A while, simultaneously, video line 2 is loaded into memory B. A time base error occurs causing video line 3 to arrive early, before memory A has finished unloading video line 1. Since both memories A and B are presently occupied, video line 3 must be loaded into the spare memory C in order to avoid conflicts between read and write operations or the loss of video data line 3. Accordingly, it is apparent that this type of system requires some device for sensing time base errors (or sensing potential memory read and write conflicts caused by time base errors) and a multiplexing device to activate the spare memory in case of such time base errors. The problem is that the addition of a spare memory and multiplexer is relatively complex and costly. It is seemingly impossible to eliminate this additional expense without running the risk of significant data losses due to conflicts between memory read and write operations caused by time base errors.